Fault Tree Analysis Constraints and Special Cases

In order to permit analysis, all fault tree diagrams created in BlockSim must conform to the following constraints:

• A diagram must contain a top gate and at least one event.
• All blocks in the diagram must be connected.
• An event can have only one output event, and no input events or gates.
• Additional gates are not allowed below a load sharing gate or standby gate.
• The inputs to negative gates (i.e., NOT, NAND and NOR gates) must be fixed probabilities, or evaluate to fixed probabilities; this is checked at analysis, and any input that evaluates to a time-varying model will result in an error, indicated with a flag applied to the gate.

Fault Tree Special Cases

For analytical fault trees, the ways in which duty cycles and mirrored event blocks interact differ depending on the analysis type used. Consequently, analysis results will differ. Consider the following example:

Here, assume that a duty cycle has been applied to one subdiagram; the FaultTree1 subdiagram block on the left has a duty cycle of 1, while the FaultTree1 subdiagram block on the right has a duty cycle of 4. If you use the Equation analysis type, the duty cycle will be applied to the right subdiagram but not the left. If you use the Binary Decision Diagram (BDD) analysis type, the duty cycle will be ignored entirely due to the mirrored event block in the subdiagram, and specifically due to the fact that the mirroring is not wholly contained within the subdiagram.